The present invention relates to a method for forming gate dielectrics, and more particularly, to an atomic layer deposition method for uniformly depositing silicon oxynitride (SiOxNy) having a low nitrogen concentration at an interface between the substrate and gate dielectric.
With decreasing gate lengths in metal oxide semiconductor field effect transistors, thin gate oxides, on the order of 2 nm or less, are necessary to increase drive currents and improve short-channel behavior. Silicon dioxide has been one of the most important and widely used materials in the microelectronics industry. One of the biggest technological challenges facing the semiconductor industry is finding a replacement gate dielectric for SiO2 for future metal oxide semiconductor field effect transistors.
Silicon oxynitride (SiOxNy) is a likely gate dielectric for future complementary metal oxide semiconductor (CMOS) devices. Layers of pure SiO2 are too limiting because SiO2 has a low dielectric constant. A long list of improved electrical properties of oxynitride films compared to SiO2 include: immunity to hot carrier effects, resistance to boron diffusion, higher charge to breakdown effects and an incremental increase in dielectric constant. Layers of pure SiN are too limiting because of the increased levels of fixed charge and mobility degradation associated with SiN. High-k dielectrics, such as HfO2, may also be limiting due to charge trapping, mobility, and cross-contamination in conventional CMOS process flows.
One reason for N incorporation into SiO2 is to increase the dielectric constant of the film. As silicon oxynitrides are scaled below 2.0 nm, it is desirable to place more N in the film in order to increase the dielectric constant. Dielectric constant is a numerical value representing the effectiveness of a non-conductive material to store electrical charge under the influence of a potential difference. Increasing the dielectric constant of the silicon oxynitride allows the film to be physically thicker, thereby reducing gate leakage current, while maintaining the same capacitance needed to meet the drive current target.
In addition to incorporating N into the film, the placement or distribution of N throughout the film is equally important. Present thermal methods leave little control over the placement of nitrogen in silicon oxynitride films. N placement in oxynitrides films has been done by thermal anneals of SiO2 in a NO, N2O, or NH3 ambient. Additionally, direct (oxy) nitridation of Si(100) can be done with NO, N2O, or NH3. Unfortunately, N placement cannot be manipulated with a single hot process step. Plasma nitridation has been shown to restrict N placement to top surfaces in thick oxynitride (â2.0 nm) films, but becomes less discriminating for sub 2.0 nm films.
Referring to FIG. 1, direct oxynitridation of Si in N2O places N 5 predominantly at the interface 2 between the Si substrate 1 and the gate dielectric 3. Similarly, nitridation of SiO(N) with NH3 anneals also places N 5 predominantly at the interface 2 between the Si substrate 1 and the gate dielectric 3. Plasma nitridation places N 5 at the top surfaces of the gate dielectric 3 and/or at the Si substrate/gate dielectric interface 2. Additionally, as oxynitrides scale below 2.0 nm, plasma nitridation becomes less exacting; a larger fraction of N 5 penetrates to the interface 2 between the Si substrate and the gate dielectric 3. Both thermal and plasma processes provide non-uniform N distributions with limited control, typically placing N 5 at the Si substrate/dielectric interface 2. This property is commonly referred to as N pile-up.
N pile-up is further illustrated in FIG. 2, which depicts the results of a Secondary Ion Mass Spectrometry (SIMS) depth profile analysis of a sample of a conventionally formed silicon oxynitride layer atop a Si substrate. The Y-axis of the graph represents the concentration of atoms in the sample and the X-axis represents the depth from the surface of the sample. Referring to FIG. 2, the Si trace-line 7 indicates that at depths greater than approximately 5.0 nm the concentration of Si atoms remains constant. The region of the sample at a depth greater than about 5.0 nm represents the Si substrate; and the region from 0 to about 5.0 nm represents the silicon oxynitride layer. The interface between the silicon oxynitride layer and the substrate is indicated by reference line 8. The N trace line 9 peaks at the interface 8 between the silicon oxynitride layer and the Si substrate, therefore exhibiting N pile-up where a high concentration of nitrogen is present between the silicon oxynitride layer and the Si substrate.
Nitrogen (N) pile-up at the gate dielectric/substrate interface can negatively impact device attributes, such as device drive current. The presence of N atoms in close proximity to the channel of the transistor may cause charge carriers passing through the channel to scatter. This scattering may be caused by the fixed charge associated with N atoms piled near the dielectric/substrate interface. The scattering phenomena are believed to be one mechanism by which charge carriers are slowed as they travel from the source to the drain of a transistor. The closer the fixed charge to the channel the worse the scattering is likely to be. Hence, N pile-up likely decreases carrier mobility.
Mobility degradation can be addressed by manipulating the N distribution (and therefore the fixed charge distribution) in the film such that there is minimal impact on the charge carriers traveling across the channel region of the transistor.
N pile-up can also negatively impact the reliability of the device. Negative bias temperature instability (NBTI) is a key reliability issue for the P-type field effect transistors (PFET). In severe cases NBTI may lead to 50-100 mV shifts in PFET threshold voltages (Vt) during normal device operation. Vt shifts can negatively impact device drive current performance.
Evidence in the prior art suggests that N pile-up is linked to NBTI. Interfacial N decreases interface state (Nit) and positive fixed charge (Qf) activation energies. Therefore, in the presence of increased interfacial N, Nit and Qf form with greater probability. Nit and Qf are believed to lead to the NBTI reliability problem that manifests itself as PFET Vt shift during PFET operation.
It would be highly desirable to provide a deposition method that produces a silicon oxynitride gate dielectric that does not exhibit N pile-up at the gate dielectric/substrate interface.